1. Field of the Invention
The present invention relates to an integrated circuit having a clock driver.
2. Description of the Prior Art
One type of integrated circuit (IC) is frequently referred to as an ASIC (Application Specific Integrated Circuit). This type is constructed of so-called "standard cells", alternatively referred to as "polycells", that implement defined circuit functions, and are laid out in a pattern which allows one polycell to easily communicate with other polycells. In this manner, a relatively complex integrated circuit may be constructed using polycell circuitry, and various ones of the polycells may then be reused in still other IC designs. This is convenient for computer-aided design, for example, wherein pre-defined polycells are stored in a software "library" that may be called upon as needed. The transistors in the polycells may be formed, for example, according to the transistor isolation technique described in U.S. Pat. No. 4,570,176 "CMOS Cell array with transistor isolation", which is co-assigned herewith. In order to facilitate the layout of the integrated circuit, the core logic of an ASIC chip is composed of many rows of polycells. The polycells typically implement the common logic functions (AND gates, OR gates, etc.), as well as providing clock drivers. However, whatever the electrical function, the polycells in the prior art have been similarly constructed in physical layout, with the transistor gates running orthogonally with respect to the row direction.
For example, referring to FIG. 1, an illustrative polycell design implemented with two metal conductor levels is shown. Each polycell row runs horizontally as viewed, whereas the transistor gate conductors (109, 116) run vertically. In the illustrative CMOS case, p-channel and n-channel transistors have source/drain regions formed in underlying n-regions and p-regions, respectively. These underlying doped regions (not shown) may be formed in a semiconductor substrate by a single-tub, twin-tub, or other production process technique as known in the art. Each gate conductor shown (109, 116) is common to both a p-channel transistor having p-type source (112, 117) and drain (110, 119) regions, and an n-channel transistor having n-type source (115, 120) and drain (113, 122) regions. Although only two pairs of transistors are shown in the row, typically dozens or more are provided in a given row. The vertical gate conductor layout (i.e., orthogonal to the row axis) was chosen in the prior art to provide for convenient inter-cell connection, and to improve the efficiency of space utilization. That is, various logic types (NAND gates, NOR gates, etc.) are easier to stack side-by-side when the transistor gates are vertical. This is due in pan to the fact that the gates of complementary transistors may be formed from a continuous conductor strip. That is, conductors 109 and 116 each serve as the gate conductor for both an n-channel and a p-channel transistor, without the necessity of a window to a metal layer for interconnection of the n-channel and p-channel gate conductors.
In providing signal and power connections to and among the various polycell transistors, the first metal level ("metal1") is typically used for power supply busses and also for intra-cell signal routing within the row, and for inter-cell routing between the rows in routing channels that are parallel to the rows. For example, V.sub.DD bus 102 and V.sub.SS bus 105 are typically implemented in metal1. The source regions contact the appropriate power supply bus by means of contact windows (111, 114, 118, 121 ) formed in the dielectric layer (not shown) overlying the source/drain regions. Furthermore, in a complementary transistor pair, a p-type source region (110) is connected to an n-type drain region (113) by means of a metal1 layer and contact windows, both not shown for clarity. The second metal level ("metal2") is typically used for inter-cell routing vertically. The positive (V.sub.DD) and ground (V.sub.SS) power supply buses (102, 105 respectively) run along (i.e., parallel to) the axis of the row for its entire length. These metal1 buses are fed from positive (V.sub.DD) and ground (V.sub.SS) metal2 buses (101,104), which run orthogonally to the rows. These latter busses, which are vertical as viewed in FIG. 1, are also referred to as "spines" herein, with the spine 101 contacting bus 102 by means of conductive vias 103, and spine 104 contacting bus 105 by means of vias 106. The vias are formed in the dielectric layer (not shown) separating the metal1 and metal2 layers in a manner known in the art.
In prior-art designs using two metal levels with orthogonal conductors, it is known to place circuitry, which may include clock drivers for example, underneath metal2 conductors, including the power supply conductors in regions 107, 108. The sources of the transistors in such circuitry could then be connected directly to the metal2 spines. This is possible because the second metal level is used for power supply distribution and vertical inter-cell connections. The horizontal inter-cell connections are typically provided by the first level metal conductors in the routing channels. However, in the case of a typical prior-art three metal-level design, the area under the metal2 V.sub.DD and V.sub.SS power supply spines are void of polycells, at least in designs that use metal2 input/output terminals to provide for inter-cell connection. That is, if the polycells in such designs were placed under the metal2 power supply spines, then the input and output terminals would be shorted to either V.sub.DD or V.sub.SS. Therefore, the area under the metal2 power supply spines may be wasted space in the three metal- level designs.
Each polycell logic gate, in performing its task, charges and/or discharges a capacitive load. The current required to charge/discharge this capacitance is supplied through the V.sub.DD /V.sub.SS metal1 buses. Furthermore, the current I.sub.1 flowing through spine 101 supplies currents 12 and 13 flowing in both the left- and right-hand portions of bus 102, respectively. In addition, still additional current components may contribute to I.sub.1 from the V.sub.DD busses in any other rows (not shown) connected to this spine. (Similarly, return current 16 is the sum of I.sub.4, I.sub.5 from bus 105, and currents from any other V.sub.SS busses connected to this spine.) Electromigration of the V.sub.DD /V.sub.SS metal1 buses, as well as the metal2 spines, is therefore a valid concern in polycell logic cells. Guidelines are often established to calculate the maximum number of polycells between two metal2 power or ground buses. These guidelines are based on an average capacitive load (fanout), operational frequency, and percent of time active, for each polycell and the V.sub.DD /V.sub.SS metal1 bus widths in the polycells.
The clock drivers noted above are circuits for distributing clock signals from one or more clocks to the polycell circuitry in the various rows. An illustrative two-stage clock driver implemented in CMOS technology is shown in FIG. 2. The p-channel transistor 21 and n-channel transistor 22 comprises a first complementary inverter stage, whereas transistors 23 and 24 comprises a second complementary inverter stage. This clock driver receives a clock signal "A" from a clock source that may be on the same, or alternatively a different, integrated circuit as the clock driver. The clock driver in turn provides an output signal "Z" for driving a desired number of polycells in one or more of the various rows. In this manner, the clock driver provides a sufficient drive signal to drive the required load, as typically determined by the magnitude of the switching current that is required to drive the load. While a two-stage design is illustrated, in some cases only a single-stage clock driver is required, while in other cases, three or more stages are used. The clock driver circuitry is different than logic circuitry in that the clock driver circuitry usually drives a load that is an order of magnitude or more greater than the load driven by any given logic polycell. Thus, the clock driver circuit requires more current than the standard polycells, increasing electromigration concerns.